FIG. 1 is a block diagram illustrating a general frequency measuring apparatus. As illustrated in FIG. 1, this circuit includes: test control section 1 for overall control and driving of various sections of the system, for outputting logic comparison patterns, and for defining the frequency of the device to be tested, DUT 3, based on a logic comparison pattern; clock generator 2 for generating reference clocks and clocks MCLK to be input into DUT 3 to be tested in accordance with the logic comparison pattern of test control section 1; counter 4 for counting the reference clocks; and latch 5 for holding the output of counter 4. The operation of this circuit will be described referring to FIG. 2.
For example, as illustrated in FIG. 2, a test will be described for a signal having a duty ratio of 50% and a frequency of 1 MHz (the period of the cycle being 1000 nano seconds), and which is output from DUT 3.
1f a signal is tested by generating a timing signal having a period of 10 nano seconds, i.e., such as with a clock signal of 10 MHz used as a reference signal, the error is 10% or more. Therefore, if an error of about 1% is to be maintained, timing signal generator 2 is required to generate a timing signal of less than 10 nano seconds, i.e., a clock signal of a frequency such as 100 MHz.
1n the case where a timing signal of 10 nano seconds, i.e., a clock of 100 MHz, is to be used, test control section 1 generates a control signal through its control logic which is supplied to clock generator 2, and clock generator 2 generates a clock with a period of 10 nano seconds. That is, a control signal is sent to clock generator 2, so that there would be generated a clock of 10 nano seconds for testing the low period from point A to point B, and for testing the high period from point B to point C. 1n accordance with this control signal, clock generator 2 generates a clock and a reference clock and sends them to counter 4, while clock MCLK is sent to DUT 3.
The counted output value of counter 4 is held by latch 5, while test control section 1 reads the data from latch 5. Thus, the generated frequency of DUT 3 is computed, and a pass or fail determination is made.
Under this condition, during the time when test clock signal TEST CLK moves from point A to point B, clock generator 2 outputs continuously reference clocks with a period of 10 nano seconds. At the moment when a 51st clock is output, the output of counter 4 changes and is held by latch 5. Based on this, the number of reference clocks up to point B can be determined.
During the time when the test clock signals vary from point B to point C, the reference clock pulses are counted in the same manner. During this operation, test control section 1 carries out the following arithmetic operation, thereby recognizing the frequency of test clock signal TEST CLK.
______________________________________ Low period of TEST CLK = No. of reference clocks output between points A and B .times. 10 ns = 50 .times. 10 ns = 500 ns High period of TEST CLK = No. of reference clocks output between points B and C = 50 .times. 10 ns = 500 ns Frequency F.sub.1 of measured test CLK: 1 cycle/(500 ns + 500 ns) = 1 MHz ______________________________________
The 1 MHz frequency thus measured is subjected to a decision as to whether it belongs to a particular frequency range or not, thereby testing the frequency of the test clock signals.
However, in such a general frequency measuring circuit, as the frequency of the test clock signal is high, the clock generator has to generate high frequency reference clocks, and a higher cost has to be incurred. Further, a decision procedure as to whether the clock signals to be tested belong to a particular frequency range is required. Therefore, the frequency measuring time is extended.